// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.1_AR67055 (win64) Build 1538259 Fri Apr  8 15:45:27 MDT 2016
// Date        : Thu May 26 01:33:48 2016
// Host        : tohoku-THINK running 64-bit Service Pack 1  (build 7601)
// Command     : write_verilog -force -mode synth_stub
//               c:/Xilinx/Vivado/project/E07-3DMatrix/E07-3DMatrix.srcs/sources_1/ip/blk_mem_ch_ring/blk_mem_ch_ring_stub.v
// Design      : blk_mem_ch_ring
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7k160tfbg676-1
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_2,Vivado 2016.1_AR67055" *)
module blk_mem_ch_ring(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[7:0],dina[63:0],douta[63:0]" */;
  input clka;
  input ena;
  input [0:0]wea;
  input [7:0]addra;
  input [63:0]dina;
  output [63:0]douta;
endmodule
