2016.1:
 * Version 13.1
 * Delivering only Verilog behavioral model.
 * Constraint(s) for Independent Clocks Distributed RAM FIFO is changed, which may issue a CDC-1 warning that can be safely ignored.
 * Output Register option is updated to offer either Embedded Register or Fabric Register or Both Embedded and Fabric Registers.
 * Updated the FIFO Generator GUI to provide Embedded Register option for Built-in FIFO when ECC mode in selected.
 * Programmable Full and Programmable Empty Threshold range has been reduced for UltraScale and UltraScale+ Built-in FIFO configurations. For more information on the exact threshold range change, refer the PG(057)
 * Programmable Full and Programmable Empty Threshold values were reset to its default values when the previous version of the core is upgraded to the latest version. This has been corrected
 * Revision change in one or more subcores

2015.4.2:
 * Version 13.0 (Rev. 1)
 * No changes

2015.4.1:
 * Version 13.0 (Rev. 1)
 * No changes

2015.4:
 * Version 13.0 (Rev. 1)
 * Fixed safety circuit related warnings in Behavioral model

2015.3:
 * Version 13.0
 * Additional safety circuit option provided for asynchronous reset configurations.
 * Delivering only VHDL behavioral model.
 * Added asymmetric port width support for 7-series Common Clock Block RAM FIFO
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

2015.2.1:
 * Version 12.0 (Rev. 4)
 * No changes

2015.2:
 * Version 12.0 (Rev. 4)
 * No changes

2015.1:
 * Version 12.0 (Rev. 4)
 * Delivering  non encrypted behavioral models.
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports
 * Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.
 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
 * Version 12.0 (Rev. 3)
 * No changes

2014.4:
 * Version 12.0 (Rev. 3)
 * Reduced DRC warnings.
 * Internal device family change, no functional changes
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time

2014.3:
 * Version 12.0 (Rev. 2)
 * Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
 * Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
 * Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.
 * Added support for Low Latency Built-in FIFO for UltraScale devices.

2014.2:
 * Version 12.0 (Rev. 1)
 * Repackaged to improve internal automation, no functional changes.

2014.1:
 * Version 12.0
 * Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.
 * Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.
 * Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices
 * Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices
 * Internal device family name change, no functional changes

2013.4:
 * Version 11.0 (Rev. 1)
 * Added support for Ultrascale devices
 * Common Clock Builtin FIFO is set as default implementation type only for UltraScale devices
 * Embedded Register option is always ON for Block RAM and Builtin FIFOs only for UltraScale devices
 * Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices

2013.3:
 * Version 11.0
 * AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.
 * AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full
 * Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth
 * Enhanced support for IP Integrator
 * Reduced warnings in synthesis and simulation
 * Added support for Cadence IES and Synopsys VCS simulators
 * Improved GUI speed and responsiveness, no functional changes
 * Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4

2013.2:
 * Version 10.0 (Rev. 1)
 * Constraints processing order changed

2013.1:
 * Version 10.0
 * Native Vivado Release
 * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

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