PulGen_top Project Status (02/12/2016 - 18:41:32)
Project File: ISE14.6.xise Parser Errors: No Errors
Module Name: PulGen_top Implementation State: Programming File Generated
Target Device: xc3s700an-4fgg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
89 Warnings (2 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 1 Failing Constraint
Environment: System Settings
  • Final Timing Score:
19846  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 4,633 11,776 39%  
Number of 4 input LUTs 4,109 11,776 34%  
Number of occupied Slices 3,610 5,888 61%  
    Number of Slices containing only related logic 3,610 3,610 100%  
    Number of Slices containing unrelated logic 0 3,610 0%  
Total Number of 4 input LUTs 4,448 11,776 37%  
    Number used as logic 3,996      
    Number used as a route-thru 339      
    Number used as 16x1 RAMs 8      
    Number used as Shift registers 105      
Number of bonded IOBs 68 372 18%  
    IOB Flip Flops 32      
Number of ODDR2s used 1      
Number of BUFGMUXs 5 24 20%  
Number of DCMs 1 8 12%  
Number of RAMB16BWEs 15 20 75%  
Average Fanout of Non-Clock Nets 3.10      
 
Performance Summary [-]
Final Timing Score: 19846 (Setup: 0, Hold: 19846, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 1 Failing Constraint    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent金 2 12 20:23:34 2016064 Warnings (1 new)29 Infos (0 new)
Translation ReportCurrent金 2 12 20:24:38 2016001 Info (0 new)
Map ReportCurrent金 2 12 20:24:50 201609 Warnings (0 new)5 Infos (1 new)
Place and Route ReportCurrent金 2 12 20:25:29 201609 Warnings (1 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrent金 2 12 20:25:38 2016006 Infos (0 new)
Bitgen ReportCurrent金 2 12 20:25:55 201607 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrent月 2 15 13:54:00 2016
WebTalk Log FileCurrent金 2 12 20:25:56 2016

Date Generated: 01/23/2017 - 16:09:07