JTAG_IF Project Status (04/22/2015 - 15:45:21)
Project File: ISE14.6.xise Parser Errors: No Errors
Module Name: JTAG_IF Implementation State: Mapped (Failed)
Target Device: xc6slx45-2fgg484
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Date 5 4 15:16:24 2014
WebTalk Log FileOut of Date 7 9 16:21:41 2014

Date Generated: 04/22/2015 - 15:51:46