Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2086221
date_generatedTue Jul 14 17:58:50 2020 os_platformWIN64
product_versionVivado v2017.4 (64-bit) project_id7b6af5bd53fc40b3910c1f8062c0299c
project_iteration271 random_id0929d5525ad35c85b118b5b32f5ecc7f
registration_id211210428_1777529957_210669243_206 route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagefgg484 target_speed-2
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-5600U CPU @ 2.60GHz cpu_speed2594 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
abstractfileview_reload=1 abstractsearchablepanel_show_search=1 basedialog_cancel=15 basedialog_no=8
basedialog_ok=1638 basedialog_yes=407 basereporttab_rerun=1 cfgmempartchooser_table=6
closeplanner_yes=9 cmdmsgdialog_ok=102 cmdmsgdialog_open_messages_view=1 commandlinepanel_command=1
copyrundialog_run_name=2 coretreetablepanel_core_tree_table=29 createconstraintsfilepanel_file_name=1 createsrcfiledialog_file_name=6
customizecoredialog_documentation=1 customizecoredialog_ip_location=1 customizeerrordialog_ok=1 editoroptions_editor_options_pane=1
expreporttreepanel_exp_report_tree_table=3 expruntreepanel_exp_run_tree_table=12 filesetpanel_file_set_panel_tree=1019 filesetpanel_messages=1
flownavigatortreepanel_flow_navigator_tree=2113 gettingstartedview_create_new_project=3 gettingstartedview_open_project=60 hacgccoefilewidget_browse=1
hacgcipsymbol_show_disabled_ports=4 hacgctabbedpane_tabbed_pane=2 hardwarecfgmemproppanels_specify_configuration_memory_programming=5 hardwaretreepanel_hardware_tree_table=170
hcodeeditor_search_text_combo_box=145 hpopuptitle_close=11 htable_set_eliding_for_table_cells=1 incrementalcompilepanel_select_checkpoint_file_to_use_as=2
instancemenu_floorplanning=1 intraclockssectionpanel_intra_clocks_section_table=1 labtoolsmenu_jtag_scan_rate=4 launchpanel_generate_scripts_only=4
launchpanel_launch_runs_on_local_host=2 mainmenumgr_edit=6 mainmenumgr_file=82 mainmenumgr_flow=8
mainmenumgr_help=2 mainmenumgr_import=1 mainmenumgr_open_recent_file=1 mainmenumgr_open_recent_project=32
mainmenumgr_report=2 mainmenumgr_settings=2 mainmenumgr_tools=4 mainmenumgr_view=10
mainmenumgr_window=2 mainwinmenumgr_layout=2 messagewithoptiondialog_dont_show_this_dialog_again=2 msgtreepanel_message_view_tree=184
msgview_information_messages=7 msgview_manage_message_suppression=1 msgview_warning_messages=12 navigabletimingreporttab_timing_report_navigation_tree=308
openfileaction_open_directory=1 openipexampledesign_example_project_directory=1 opentargetwizard_connect_to=2 optionsview_close=1
overwriteconstraintsdialog_overwrite=14 packagetreepanel_package_tree_panel=2 pacodeeditor_goto_definition=1 pacommandnames_add_config_memory=7
pacommandnames_add_sources=8 pacommandnames_auto_connect_target=31 pacommandnames_auto_update_hier=13 pacommandnames_bitstream_settings=13
pacommandnames_close_server=72 pacommandnames_close_target=4 pacommandnames_create_hardware_dashboards=3 pacommandnames_goto_implemented_design=38
pacommandnames_goto_instantiation=2 pacommandnames_goto_netlist_design=12 pacommandnames_impl_settings=23 pacommandnames_log_window=1
pacommandnames_open_hardware_manager=17 pacommandnames_open_ip_example_design=2 pacommandnames_open_project=38 pacommandnames_open_target=2
pacommandnames_open_target_wizard=144 pacommandnames_program_config_memory=33 pacommandnames_program_fpga=2 pacommandnames_refresh_server=2
pacommandnames_refresh_target=1 pacommandnames_reports_window=2 pacommandnames_run_bitgen=82 pacommandnames_run_implementation=8
pacommandnames_save_design=31 pacommandnames_select_area=1 pacommandnames_simulation_run=2 pacommandnames_toggle_view_nav=2
pacommandnames_write_config_memory_file=5 pacommandnames_zoom_fit=3 partchooser_parts=1 pathreporttableview_description=2
paviews_code=79 paviews_ip_catalog=6 paviews_path_table=2 paviews_schematic=20
portmenu_configure_io_ports=1 portmenu_reset_port_properties=2 powerresulttab_report_navigation_tree=1 programcfgmemdialog_address_range_used_for_erase_blank=2
programcfgmemdialog_contents_of_configuration_file=24 programcfgmemdialog_memory_device=2 programcfgmemdialog_specify_prm_file=2 programdebugtab_open_recently_opened_target=181
programdebugtab_open_target=14 programdebugtab_program_device=1 programdebugtab_refresh_device=1 programfpgadialog_program=283
programfpgadialog_specify_bitstream_file=31 programoptionspanelimpl_strategy=15 progressdialog_background=11 progressdialog_cancel=1
projectnamechooser_project_name=2 projecttab_close_design=1 projecttab_reload=1 quickhelp_help=2
rdicommands_delete=5 rdicommands_properties=5 rdicommands_redo=17 rdicommands_save_file=1092
rdicommands_undo=576 reportnavigationholder_save=1 rungadget_show_warning_and_error_messages_in_messages=1 saveprojectutils_cancel=1
saveprojectutils_save=43 searchcommandcomponent_quick_access=2 selectmenu_highlight=15 selectmenu_mark=9
settingsprojectrunpage_choose_report_strategy=4 signaltreepanel_expand_selected_rows=1 signaltreepanel_signal_tree_table=726 simpleoutputproductdialog_generate_output_products_immediately=80
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1 srcchooserpanel_add_or_create_source_file=1 srcchooserpanel_create_file=7 srcmenu_ip_documentation=6
srcmenu_ip_hierarchy=10 stalemoreaction_out_of_date_details=1 stalerundialog_open_design=2 stalerundialog_yes=8
statemonitor_reset_run=13 statemonitor_reset_step=1 syntheticagettingstartedview_recent_projects=2 syntheticastatemonitor_cancel=45
targetchooserpanel_add_xilinx_virtual_cable_as_hardware=3 targetchooserpanel_target_chooser_table=14 tclconsoleview_tcl_console_code_editor=1 timingitemflattablepanel_floorplanning=1
timingitemflattablepanel_table=53 upgradeprojectdialog_open_project_in_read_only_mode=1 writecfgmemfiledialog_custom_memory_size=3 writecfgmemfiledialog_daisy_chain_configuration_file=4
writecfgmemfiledialog_format=5 writecfgmemfiledialog_interface=2 writecfgmemfiledialog_load_bitstream_files=5 writecfgmemfiledialog_load_data_files=3
writecfgmemfiledialog_memory_part=5 writecfgmemfiledialog_overwrite=3 writecfgmemfiledialog_part_chooser=1 writecfgmemfiledialog_specify_configuration_filename=20
writecfgmemfiledialog_write_checksum=2 xpg_ipsymbol_show_disabled_ports=1
java_command_handlers
addcfgmem=6 addsources=10 autoconnecttarget=31 closeproject=14
closeserver=72 closetarget=4 coreview=11 customizecore=9
editdelete=5 editpaste=9 editproperties=5 editundo=8
fileprintcmdhandler=1 launchopentarget=145 launchprogramfpga=289 newhardwaredashboard=1
newproject=3 openhardwaremanager=548 openipexampledesign=2 openproject=97
openrecenttarget=188 opentarget=1 programcfgmem=38 programdevice=317
recustomizecore=109 refreshdevice=1 refreshserver=2 refreshtarget=1
reportclockinteraction=1 reportclocknetworks=2 reportdrc=3 reportmethodology=1
reporttimingsummary=5 reportutilization=2 runbitgen=335 runimplementation=383
runschematic=25 runsynthesis=98 savedesign=31 showpowerestimation=4
showsource=2 showview=284 tclfind=1 timingconstraintswizard=4
toggleselectareamode=1 toggleviewnavigator=2 toolssettings=41 viewtaskimplementation=205
viewtaskprogramanddebug=2 viewtaskprojectmanager=78 viewtaskrtlanalysis=1 viewtasksynthesis=17
writecfgmemfile=7 zoomfit=3
other_data
guimode=165
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_2 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=62 export_simulation_ies=62
export_simulation_modelsim=62 export_simulation_questa=62 export_simulation_riviera=62 export_simulation_vcs=62
export_simulation_xsim=62 implstrategy=Performance_Retiming launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=2 simulator_language=Mixed srcsetcount=14 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=2 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=11 carry4=353 fdce=892 fdpe=104
fdre=5189 fdse=93 gnd=302 ibuf=68
lut1=478 lut2=1024 lut3=1405 lut4=617
lut5=652 lut6=1282 mmcme2_adv=2 muxf7=129
muxf8=48 obuf=38 obuft=5 obuftds=32
ramb18e1=5 ramb36e1=9 rams32=8 srl16e=71
srlc16e=71 vcc=13 xadc=1
pre_unisim_transformation
bufg=11 carry4=353 fdce=892 fdpe=104
fdre=5189 fdse=93 gnd=302 ibuf=69
iobuf=1 lut1=478 lut2=1024 lut3=1405
lut4=617 lut5=652 lut6=1282 mmcme2_adv=2
muxf7=129 muxf8=48 obuf=38 obuft=4
obuftds=32 ram32x1s=8 ramb18e1=5 ramb36e1=9
srl16e=71 srlc16e=71 vcc=13 xadc=1

phys_opt_design_post_place
command_line_options
-bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified] -critical_pin_opt=default::[not_specified]
-directive=AlternateFlowWithRetiming -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified] -fanout_opt=default::[not_specified]
-hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified] -placement_opt=default::[not_specified]
-restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified] -shift_register_opt=default::[not_specified]
-uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=35 bram_ports_total=28 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=6157 srls_augmented=0
srls_newly_gated=0 srls_total=71

ip_statistics
clk_wiz_v5_4_3_0/1
clkin1_period=25.000 clkin2_period=10.0 clock_mgr_type=NA component_name=clk_wiz_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=4 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
clk_wiz_v5_4_3_0/2
clkin1_period=25.000 clkin2_period=10.0 clock_mgr_type=NA component_name=clk_wiz_1
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=4 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
xadc_wiz_v3_3_5/1
channel_averaging=None component_name=xadc_wiz_0 core_container=false dclk_frequency=200
enable_axi=false enable_axi4stream=false enable_busy=true enable_convst=false
enable_convstclk=false enable_dclk=true enable_drp=true enable_eoc=true
enable_eos=true enable_vbram_alaram=false enable_vccaux_alaram=false enable_vccddro_alaram=false
enable_vccint_alaram=false enable_vccpaux_alaram=false enable_vccpint_alaram=false iptotal=1
ot_alaram=false sequencer_mode=on startup_channel_selection=contineous_sequence timing_mode=continuous
user_temp_alaram=false

report_design_analysis
command_line_options
-append=default::[not_specified] -bounding_boxes=default::[not_specified] -cells=default::[not_specified] -complexity=default::[not_specified]
-congestion=default::[not_specified] -end_point_clock=default::[not_specified] -extend=default::[not_specified] -extract_metrics=default::[not_specified]
-file=[user-defined] -full_logical_pin=default::[not_specified] -hierarchical_depth=default::[not_specified] -hold=default::[not_specified]
-logic_level_dist_paths=default::[not_specified] -logic_level_distribution=[specified] -logic_levels=default::[not_specified] -max_level=default::[not_specified]
-max_paths=default::[not_specified] -min_level=default::[not_specified] -name=default::[not_specified] -no_header=default::[not_specified]
-of_timing_paths=default::[not_specified] -pploc_distance=default::[not_specified] -qor_summary=default::[not_specified] -quiet=default::[not_specified]
-return_string=default::[not_specified] -return_timing_paths=default::[not_specified] -routed_vs_estimated=default::[not_specified] -routes=default::[not_specified]
-setup=default::[not_specified] -suggestion=default::[not_specified] -timing=default::[not_specified] -verbose=default::[not_specified]
flow_sequence
task=opt_design
usage
runtime=0.476 secs
usage_count
file=1 logic_level_distribution=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 check-3=1 plholdvio-2=1 reqp-1839=12
reqp-1840=20

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-10=1 timing-14=1 timing-17=1000 timing-18=72
timing-27=2 timing-28=6 timing-6=4 timing-9=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=11 bufgctrl_util_percentage=34.38
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=2 mmcme2_adv_util_percentage=33.33
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=240 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=1 lvcmos33=1 lvds_25=1
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=11.5 block_ram_tile_util_percentage=8.52
ramb18_available=270 ramb18_fixed=0 ramb18_used=5 ramb18_util_percentage=1.85
ramb18e1_only_used=5 ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=9
ramb36_fifo_util_percentage=6.67 ramb36e1_only_used=9
primitives
bufg_functional_category=Clock bufg_used=11 carry4_functional_category=CarryLogic carry4_used=344
fdce_functional_category=Flop & Latch fdce_used=840 fdpe_functional_category=Flop & Latch fdpe_used=96
fdre_functional_category=Flop & Latch fdre_used=5128 fdse_functional_category=Flop & Latch fdse_used=93
ibuf_functional_category=IO ibuf_used=66 lut1_functional_category=LUT lut1_used=264
lut2_functional_category=LUT lut2_used=1005 lut3_functional_category=LUT lut3_used=1354
lut4_functional_category=LUT lut4_used=609 lut5_functional_category=LUT lut5_used=639
lut6_functional_category=LUT lut6_used=1188 mmcme2_adv_functional_category=Clock mmcme2_adv_used=2
muxf7_functional_category=MuxFx muxf7_used=129 muxf8_functional_category=MuxFx muxf8_used=48
obuf_functional_category=IO obuf_used=38 obuft_functional_category=IO obuft_used=5
obuftds_functional_category=IO obuftds_used=32 ramb18e1_functional_category=Block Memory ramb18e1_used=5
ramb36e1_functional_category=Block Memory ramb36e1_used=9 rams32_functional_category=Distributed Memory rams32_used=8
srl16e_functional_category=Distributed Memory srl16e_used=71 xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=129 f7_muxes_util_percentage=0.41
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=48 f8_muxes_util_percentage=0.30
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=8 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=4592 lut_as_logic_util_percentage=7.24 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=57 lut_as_memory_util_percentage=0.30 lut_as_shift_register_fixed=0 lut_as_shift_register_used=49
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=6157 register_as_flip_flop_util_percentage=4.86
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=4649 slice_luts_util_percentage=7.33
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=6157 slice_registers_util_percentage=4.86
fully_used_lut_ff_pairs_fixed=4.86 fully_used_lut_ff_pairs_used=269 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=8
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_used=4592 lut_as_logic_util_percentage=7.24
lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_used=57 lut_as_memory_util_percentage=0.30
lut_as_shift_register_fixed=0 lut_as_shift_register_used=49 lut_ff_pairs_with_one_unused_flip_flop_fixed=49 lut_ff_pairs_with_one_unused_flip_flop_used=2403
lut_ff_pairs_with_one_unused_lut_output_fixed=2403 lut_ff_pairs_with_one_unused_lut_output_used=2633 lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=2950 lut_flip_flop_pairs_util_percentage=4.65 slice_available=15850 slice_fixed=0
slice_used=1998 slice_util_percentage=12.61 slicel_fixed=0 slicel_used=1360
slicem_fixed=0 slicem_used=638 unique_control_sets_used=335 using_o5_and_o6_fixed=335
using_o5_and_o6_used=22 using_o5_output_only_fixed=22 using_o5_output_only_used=25 using_o6_output_only_fixed=25
using_o6_output_only_used=2
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=1 xadc_used=1 xadc_util_percentage=100.00

router
usage
actual_expansions=6935930 bogomips=0 bram18=5 bram36=9
bufg=0 bufr=0 congestion_level=0 ctrls=335
dsp=0 effort=2 estimated_expansions=6843078 ff=6157
global_clocks=11 high_fanout_nets=7 iob=170 lut=4818
movable_instances=12296 nets=14333 pins=65993 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a100tfgg484-2
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=Top -verilog_define=default::[not_specified]
usage
elapsed=00:01:46s hls_ip=0 memory_gain=647.941MB memory_peak=941.594MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::