| top Project Status (01/09/2015 - 01:31:44) | |||
| Project File: | multi_chip.xise | Parser Errors: | X 1 Error |
| Module Name: | conf_maker | Implementation State: | Programming File Not Generated |
| Target Device: | xc4vlx25-10ff668 |
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| Product Version: | ISE 14.4 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: |
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| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | ||||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Thu Jan 8 09:58:46 2015 | |
| WebTalk Report | Out of Date | Fri Jan 9 01:31:36 2015 | |
| WebTalk Log File | Out of Date | Fri Jan 9 01:31:44 2015 | |