top Project Status (02/03/2017 - 15:18:07) | |||
Project File: | multi_chip.xise | Parser Errors: | No Errors |
Module Name: | top | Implementation State: | Programming File Generated |
Target Device: | xc5vlx50-1ff676 |
|
No Errors |
Product Version: | ISE 14.4 |
|
182 Warnings (2 new) |
Design Goal: | Balanced |
|
All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
|
All Constraints Met |
Environment: | System Settings |
|
0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Registers | 2,361 | 28,800 | 8% | ||
Number used as Flip Flops | 2,361 | ||||
Number of Slice LUTs | 2,505 | 28,800 | 8% | ||
Number used as logic | 2,485 | 28,800 | 8% | ||
Number using O6 output only | 1,997 | ||||
Number using O5 output only | 253 | ||||
Number using O5 and O6 | 235 | ||||
Number used as Memory | 1 | 7,680 | 1% | ||
Number used as Shift Register | 1 | ||||
Number using O6 output only | 1 | ||||
Number used as exclusive route-thru | 19 | ||||
Number of route-thrus | 272 | ||||
Number using O6 output only | 272 | ||||
Number of occupied Slices | 1,174 | 7,200 | 16% | ||
Number of LUT Flip Flop pairs used | 3,281 | ||||
Number with an unused Flip Flop | 920 | 3,281 | 28% | ||
Number with an unused LUT | 776 | 3,281 | 23% | ||
Number of fully used LUT-FF pairs | 1,585 | 3,281 | 48% | ||
Number of unique control sets | 162 | ||||
Number of slice register sites lost to control set restrictions |
278 | 28,800 | 1% | ||
Number of bonded IOBs | 137 | 440 | 31% | ||
Number of LOCed IOBs | 137 | 137 | 100% | ||
IOB Flip Flops | 56 | ||||
Number of BlockRAM/FIFO | 31 | 48 | 64% | ||
Number using BlockRAM only | 31 | ||||
Number of 18k BlockRAM used | 56 | ||||
Total Memory used (KB) | 1,008 | 1,728 | 58% | ||
Number of BUFG/BUFGCTRLs | 15 | 32 | 46% | ||
Number used as BUFGs | 15 | ||||
Number of IDELAYCTRLs | 3 | 16 | 18% | ||
Number of DCM_ADVs | 5 | 12 | 41% | ||
Number of RPM macros | 26 | ||||
Average Fanout of Non-Clock Nets | 4.38 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fri Feb 3 15:15:34 2017 | 0 | 116 Warnings (0 new) | 49 Infos (0 new) | |
Translation Report | Current | Fri Feb 3 15:15:45 2017 | 0 | 58 Warnings (2 new) | 9 Infos (0 new) | |
Map Report | Current | Fri Feb 3 15:16:28 2017 | 0 | 6 Warnings (0 new) | 14 Infos (0 new) | |
Place and Route Report | Current | Fri Feb 3 15:17:02 2017 | 0 | 1 Warning (0 new) | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Fri Feb 3 15:17:20 2017 | 0 | 1 Warning (0 new) | 4 Infos (0 new) | |
Bitgen Report | Current | Fri Feb 3 15:17:45 2017 | 0 | 0 | 5 Infos (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Mon Jun 20 00:46:23 2016 | |
WebTalk Report | Current | Fri Feb 3 15:17:47 2017 | |
WebTalk Log File | Current | Fri Feb 3 15:18:07 2017 |