top Project Status (01/09/2015 - 01:31:44)
Project File: multi_chip.xise Parser Errors: X 1 Error
Module Name: conf_maker Implementation State: Programming File Not Generated
Target Device: xc4vlx25-10ff668
  • Errors:
 
Product Version:ISE 14.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu Jan 8 09:58:46 2015
WebTalk ReportOut of DateFri Jan 9 01:31:36 2015
WebTalk Log FileOut of DateFri Jan 9 01:31:44 2015

Date Generated: 01/09/2015 - 01:44:45