FPGA training course 2025@SOKENDAI, KEK, English

   

This is a hand-on seminar for participants without experience of using FPGA tools. The major content is utilizing the development tools for FPGA digital circuit design, and we expect that the minimal knowledge will be provided such that the participants will become able to continue with self-learning afterwards.

 

The target audience is mainly students without experience of electornics engineering or FPGA digital circuit development, and the course is designed to aim for students majoring experimental physics, but students and researchers from the other fields are also welcome. 

 

Regarding the necessary knowledge for FPGA circuit development: 

(1) Knowledge about the digital circuit design

(2) Implementation on FPGA

For (1), there are some textbooks for self-learning, but there is no such good way to learn about (2), which will be introduced in this seminar.

After participating this seminar, you are expected to be able to design your own digital circuit and to implement it on FPGA, so the learning efficiency on (1) will be also improved.

 

The FPGA device used in the practice is AMD Xilinx Artix-7 series, and we will use Verilog-HDL. The development tool is AMD Xilinx Vivado (ML) 2023.1.

 

Notice: About distributing the texts only:

We do not only distribute the texts for the course. Since the texts are made to help the explanation the content during the course, not for self-learning purpose. If we share only the texts, it will confuse and cause misunderstanding for users.

 

 

Field Prgrammable Gate Arrays (FPGA) is a user-programmable digital circuit.
 

Recently, it is widely used in the readout system of radiation detector. The circuit scale of single FPGA becomes very large such that a large amount of user-designed signal processing circuits can be implemented in a single chip. For instance, it is possible to implement a circuitto embed a CPU and run a Linux OS on a single chip.

 

  

• Target: Students from SOKENDAI and other institutes, researchers, staffs, technical staffs.
  • Only for Japanese residents who are currently affiliated with institutions and universities in Japan.
• About the course credit 
  • 【For SOKENDAI students】: This course is a two-day intensive course (集中講義) offered as "Basic digital circuit design and development for measurement and control systems" at SOKENDAI. With proper registration procedures, students can obtain credit for their courses (1 credit) and travel expenses for participation from SOKENDAI.
    
    • About course registration
      • Students who have already registered for courses should should also register using the online form (same as the one below). 
      • Students who wish to register for additional courses must obtain approval from their primary supervisor before registering the online form. Additional course registration will be handled by the administrative office.
      • Students who do not wish to register for courses (for auditing purpose only, not for credits) should also register by using the online form. 
      • Contact: National Institute for Fusion Science, Research Support Division, Graduate Student Affairs Section
        Tel: 0572-58-2042/2843
        Email: daigakuin(at)nifs.ac.jp <- Repalce (at) with ＠
        
        
    • About application for student's travel expenses
      
      • Details are here
      • If you would like to receive travel expenses, please make separate application to the graduate school office in your program/department (not only for this training course).
         
  • 【For students from other institutes】: This course is available to students from institutes regardless of the credit transfer agreement. If you would like to obtain credits, please contact SOKENDAI 学務課教務係 below by 7/04.
    • It is possible that the credit can not be given depending on your university.
    • Contact: SOKENDAI 学務課教務係
      Tel: 046-858-1582
      Email: kyomu(at)ml.soken.ac.jp  <- Repalce (at) with ＠
• Date: 2025/09/04 (Thu.) ~ 2025/09/05 (Fri.), 9:30-17:30
• Venue: KEK, Tsukuba campus, 先端計測開発棟 (Advanced Instrumentation Lab.(2)), R208. 
  Please find "I17" KEK Tsukuba campus map: https://www2.kek.jp/rso/Map/pdf/kek_map.pdf
  • Only in-person attendance is accepted. We do not provide remote attendance.

• Deadline of application: 2025/08/04
• Number of attendants: 20 people.
• Language: English.
• Tuition fee: free
• Accomendation: To use KEK dormitory, please make sure if you have registered as a KEK user: https://krs.kek.jp/uskek/ui/UI_00000E.do
  You can refer to here about registration as a KEK user for this event.
  Otherwise, there is hotel nearby KEK (Oho, Chikuho regions).
• Host: KEK
• Support: Open-It
• Manager: Yun-Tsung Lai (KEK, SOKENDAI) 
  Please contact ytlai(at)post.kek.jp if you have any question.

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Application

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• Please go to this page to register.
    

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Details

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• Lecturer: Yun-Tsung Lai (KEK, SOKENDAI)
• Preparation: Unfortunately, this document for preview is only in Japanese. You can also refer to the lecture material. We will do a review also in the beginning of the course. 
  • Preview (PDF) in Japanese.
  • You can also refer to this slide, which will be released about 1 week before the course.
• During prcatice, we will use a Xilinx Artix-7 series FPGA. We will use Verilog-HDL, and the development tools is ilinx (AMD) Vivado ML 2023.1.
• To use the board for practice (Digilent Nexys4), we will provide the cable for USB Type-A/Micro Type-B, so no need to prepare it.
• Preparation and the stuffs which you need to bring
  • Laptop
    • Vivado ML 2023.1 installed, with a USB Type-A port, Windows PC.
    • Linux is also fine, but please check the details of environment and installation below.
      
      • We will not prepare spare laptops, so you cannot do anything without bringing your own laptop, then we cannot give credit.
      • Notice: We do not recommend using Apple MAC to install Vivado. There might be some special way to do so, but none of them are guaranteed by Xilinx technically, so as the organizers of this course. 
    • About Xilinx (AMD) Vivado ML 2023.1 tool
      • Please refer to this manual to install it. The installation method for MAC and Linux is also written.
      • Information from Xilinx is here (Xilinx Webpage).
    • Requirement for the system.
      • OS：Windows 10, 11, 64 bits (cannot run in 32-bits)
      • Memory: 2GB (recommended to be 4GB)
      • USB Type-A  port is needed. If there is only Type-C, please bring your own USB Type-C/Micro Type-B (2.0) adapter cable.
      • Please refer to this (Xilinx Webpage) for more requirements from Xilinx.
  • Bring your own notetaker. 
  • Print out the following documents for practice. No need to read them beforehand. If you don't print them our, it is not so covenient to read them in the same leptop during the coruse.
    • Reference for practice
    • Manual for practice C1
    • Manual for practice S1
    • Manual for practice I1
    • Manual for practice I2
    • Introduction to Verilog-HDL

Program

Material

• 0. Introduction
• 1. Review
• 2.1 [Cobinational circuit] Verilog-HDL description
• 2.2 [Combinational circuit] HDL input and RTL analysis in Vivado
• 2.3 [Combinational circuit] Logic simulation using Vivado
• 2.4 [Combinational circuit] Implementation on FPGA using Vivado
• 3  [Combinational circuit] Design practice
• 4.1 [Sequential circuit] Verilog-HDL description
• 4.2 [Sequential circuit] Logic simulation using Vivado
• 4.3 [Sequential circuit] Implementation on FPGA using Vivado
• 5. [Sequential circuit] Design practice
• 6. Hierarchical structure design
• 7. IPcore
• 8. Design practice (summary)
• 9. Booting from external memory (Reference material: not used in the course)
• A. Other reference (Reference material: not used in the course)

• Circuit schematics of the board used in practice (Digilent Webpage)
• Reference manual of the circuit board used in the practice (Digilent Webpage)

Questionaire