FPGA advanced training course 2025@Sokendai KEK, English
Purpose
This seminar aims to introduce the advanced techniques of FPGA firmware making for the experimental physics purpose.
The target for participants is to understand the functionalities of Xilinx FPGA and to be able to implement the specific processing logic required for experimental purpose.
The course is intended for students with about one year of experience of developing FPGA firmware in experimental projects, particularly targeted at students from physics laboratory. But students and young researchers in other fields are also welcome.
Notice: It is not intended for:
- Beginners with little or no experience, or
- Those who just recently took a fundamental FPGA training course
to take this course.
The purpose of this course is basically the same as the one of fundamental FPGA course for beginners:
1. Knowledge about digital circuit design
2. How to implement in FPGA
The principles of processing algorithm can be learned by reading books and papers, but implementation on a specific FPGA requires knowledge of the built-in functions of the FPGA.The The user guides provided by Xilinx (UG) are difficult to understand for users with about one year experience, and are usually lengthy. This is one of the reasons why FPGA design is considered as a difficult technique to be learned.
Therefore, this seminar aims to fill the gap between training course and actual development, and will cover the built-in functions of Xilinx FPGAs in our lectures and exercises.
Therefore, this seminar aims to fill the gap between training course and actual development, and will cover the built-in functions of Xilinx FPGAs in our lectures and exercises.
In our practice, we will use Xilinx Kintex-7 series of FPGA. The programming language is Verilog-HDL or VHDL. The development software tool is Xilinx Vivado WebPACK.
Notice: about the distribution of the teaching material
Our teaching materials are only for explanation on the practice. They are not intended to be utilized for self-learning. Distributing the materials might cause misunderstanding for other readers, and it is also against the intention of the organizers. Please do not distribute them.
Overview
- Targer: Students from Sokendai and other institutes, researchers, staffs, technical staffs with at least one year of experience in FPGA firmware making.
- Those who have taken FPGA training courses and measurement and control courses (計測と制御) or have a significant amount of knowledge.
- Or those who have about one year of experience in FPGA firmware making.
- Those who have taken FPGA training courses and measurement and control courses (計測と制御) or have a significant amount of knowledge.
- About the course credit
- 【For Sokendai students】: This course is a three-day intensive course (集中講義) offered as a common subject in the Particle and Nuclear Studies course at SOKENDAI. With proper registration procedures, students can obtain credit for their courses (1 credit) and travel expenses for participation from Sokendai.
- About course registration
- The self-registration period has ended. If you would like to register for additional courses, please contact the KEK department below (研究協力課大学院教育係) for separate registration other than your application for this course.
- KEK 研究協力課大学院教育係
Tel:029-864-5128
Email: kyodo2(at)mail.kek.jp <- Replace (at) with @
- About application for student's travel expenses
- Details are here
- If you would like to receive travel expenses, please make separate application to the graduate school office in your course (not only for this training course).
- About course registration
- 【For students from other institutes】: This course is available to students from institutes regardless of the credit transfer agreement. If you would like to obtain credits, please contact Sokendai 学務課教務係 below by 06/02.
- It is possible that the credit can not be given depending on your university.
- If you need credit, please contact us as soon as possible.
- Sokendai 学務課教務係
Tel:046-858-1582
Email: kyomu(at)ml.soken.ac.jp <- Replace (at) with @
- 【For Sokendai students】: This course is a three-day intensive course (集中講義) offered as a common subject in the Particle and Nuclear Studies course at SOKENDAI. With proper registration procedures, students can obtain credit for their courses (1 credit) and travel expenses for participation from Sokendai.
- Date: 2025/09/08 (Mon.) ~ 2025/09/10 (Wed.), 3 days, 9:30-17:30
- Venue: KEK Tsukuba campus, Advanced Instrumentation Lab.(2) R208 (先端計測開発棟 R208)
- Please find "I17" at the campus map.
- Number of attenders: 10 people (Due to the limited number of devices for use, the registration will be closed)
- Language for lecture give: English
- Tuition: Free
- Period for application acceptance:
- Sokendai students, or those who don't need credit: 2025/04/26 ~ 2025/07/22
- Students of other institutes with request to obtain credit: 2025/04/26 ~ 2025/06/02
- Host: Sokendai, Particle and Nuclear Physics course, KEK
- Support: Open-It
- Manager: Yun-Tsung Lai (KEK)
Please contact ytlai(at)post.kek.jp if you have any question. <- Repalce (at) with @
- Accomendation: To use KEK dormitory, please make sure if you have registered as a KEK user: https://krs.kek.jp/uskek/ui/UI_00000E.do
You can refer to here about registration as a KEK user for this event.
Otherwise, there is hotel nearby KEK (Oho, Chikuho regions).
Details
- Lecturer: Yun-Tsung Lai (KEK, Sokendai)
- In our practice, we will use Xilinx Kintex-7 series of FPGA. The programming language is Verilog-HDL or VHDL. The development software tool is Xilinx Vivado WebPACK.
- We will use Vivado 2023.
- We will prepare the FPGA devices for attenders, so no need to prepare by yourself.
- Preparation and the stuffs which you need to bring
- Laptop
- Please make sure to install Vivado WebPACK as mentioned below in your PC.
Otherwise, you can not do any practice during the source.
- We will not prepare spare PCs.
- Please be sure to bring a PC with a USB-A port.
- Please notice that, you can not do any practice if you don't bring your PC.
- Xilinx Vivado WebPack has to be installed.
- Requirement for the system
- Please prepare the development environment which you are used to.
- We will use Vivado 2023 for practice.
- Please make sure to install Vivado WebPACK as mentioned below in your PC.
- Bring your own notetaker.
- Laptop
Program
- First day, 9/8 (Mon.), 9:30-17:30
- 9:30-10:00 Introduction
- 10:00-12:00 Xilinx FPGA's stucture
- 12:00-13:00 Lunch break (60 min)
- 13:00-14:30 Arithmetics
- 14:40-16:10 IOSERDES
- 16:20-17:00 Memory resource, first part
- Second day, 9/9 (Tue.), 9:30-17:30
- 9:30-10:30 Memory resource, second part
- 10:40-12:00 GT(X) transceiver, first part
- 12:00-13:00 Lunch break (60 min)
- 13:00-14:30 GT(X) transceiver, second part
- 14:40-16:10 Constraint and some frequently met trouble, first part
- 16:20-17:00 Constraint and some frequently met trouble, second part
- Third day, 9/9 (Wed.), 9:30-17:30
- Practice
For the content of the source, it may be different from this schedule.
Text
Will be uploaded one week before the seminar.